データパス合成における最小遅延補正演算器数の最小化手法

摘要

As the feature size of VLSI becomes smaller, delay variations become a serious problem in VLSI design. The "setup" timing constraint can be fulfilled by choosing a clock period appropriately, while the "hold" timing constraint can not, and in many cases, the hold constraint becomes critical for a correct latch of a signal under delay variations. An approach to ensure the hold constraint under delay variations is to enlarge the minimum path delay between registers. It can be done by inserting delay elements on non-critical paths mainly in a functional unit. We call it "minimum path delay compensation" in this paper. The RT-level optimization problem to minimize the number of functional units which require minimum path delay compensation in datapath synthesis has been proposed, and its NP-hardness has been shown. For this problem, we propose two new methods, one is based on integer linear programming (ILP), the other is based on heuristic. We evaluate their performance by computational experiments.%半導体プロセスの微細化に伴い，製造時に生じる物理的パラメータの変動や動作時の変動に起因する遅延ばらつきの問題が深刻化している．遅延ばらつきが存在する下でデータパス回路がホールド条件を満足するための一手法として．レジスタ間の最小パス遅延を補正する手法が考えられる．これは演算器の非クリティカルパスに遅延素子を挿入することで実現されるが，最小パス遅延を補正する演算器の個数を最小化する問題がNP困難であることが示されている．本稿ではこの問題に対して整数計画法を用いて厳密解を求める手法と必ずしも最適解を得られないが効率的に解を求める発見的な手法を提案し，計算機実験により提案手法の有効性を評価する．