Sub-10 nm Multi-Nano-Pillar Type Vertical MOSFET

摘要

The excellent performance of 10nm gate Multi-Nano-Pillar type (M-) Vertical MOSFET has been numerically shown for the first time. It is made clear that M-Vertical MOSFET, in comparison with the conventional Single Pillar type (S-) Vertical MOSFET, achieve an increased driving current by more than 2 times, a nearly ideal S-factor, and a suppressed cutoff-leakage current by less than 1/60 by suppressing short channel effect and by suppressing the DIBL effect. Moreover, mechanisms of these improvements of the M-Vertical MOSFET are made clear. From all of the above, it is shown that M-Vertical MOSFET is a key device candidate for future high speed and low power LSI's in the sub-10nm generation.