block－LIMに基づくCMOS素子を含む大規模回路網の高速解析手法

摘要

非線形能動素子を含む大規模回路網の解析に対して，従来の行列演算に基づくSPICE系シミュレーションでは，莫大な計算コストを必要とする.大規模線形回路網を高速・高精度に解析する手法として，block-Latency Insertion Method （block-LIM）が提案されている.block-LIM はSPICE系シミュレータと比較して数十倍から数百倍の高速な解析が可能である．しかしながら，非線形能動回路へblock-LIMを応用した報告例はない．本稿では，block-LIMのアルゴリズムを拡張し，CMOS回路を含む大規模回路解析へ応用するための手法を提案し，その評価を行う．%For an analysis of large networks including nonlinear active devices and coupled elements, conventional SPICE-like simulators suffer from a large amount of computational cost due to time-consuming direct matrix operations. In order to overcome the problem, the block-latency insertion method (block-LIM) has been proposed as a fast circuit simulation technique. The advantage of the block-LIM is employing a local matrix operation. However, there are few applications of the block-LIM to the nonlinear circuit simulation. In this report, we describe an efficient nonlinear circuit simulation technique by using a nonlinear version of block-LIM, and estimate its characteristics by analyzing to some example nonlinear circuits.