Line Sharing Cache: Exploring Cache Capacity with Frequent Line Value Locality

摘要

The number of cores on a chip is increasing due to the continuous trend of CMOS scaling; this makes the well known memory wall problem more serious, since the amount of off-chip bandwidth available for each core keeps decreasing. In order to alleviate this problem, intelligent designs and managements of last-level cache (LLC) which attempt to reduce the number of misses and the off-chip memory accesses is becoming more and more important. This paper proposes a new LLC architecture called line sharing cache (LSC) which reduces the number of misses without increasing the size of the cache memory. The key observation used in LSC is that large amount of lines in conventional caches are filled with identical values. Conventional caches store each cache line to different data entries based on their addresses, and therefore many lines which have the exact same value are stored all over the cache memory. As a result, it wastes many transistors by having multiple identical values. LSC stores lines which have an identical value in a single data entry and allows greater amounts of lines to be stored, leading to substantial reduction in the number of cache misses. The evaluation results show performance improvement of up to 32% across a set of SPEC CPU2000 benchmarks.