We report on the design considerations of stationary-head multi-track magnetic recorders. We focus on the particular reasons for adopting the rate 8/10, DC-free recording code, the full-response detection method, and the clock recovery circuitry. Implementation issues of the channel chip, particularly related to cost and power consumption, are addressed. A new multi-track phase-lock loop (PLL) has been developed, in order to improve the recorder's robustness against time-base variations.
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