A Constrained Layout Placement Approach to Enhance Pulse Quenching Effect in Large Combinational Circuits

摘要

A novel constrained layout placement approach is proposed to enhance the pulse quenching effect in combinational circuits. This constrained algorithm can enlarge the number of quenching cells and shrink the distance between these cells. Simulation results illustrate that the soft error vulnerabilities are effectively reduced by adopting this novel constrained layout placement algorithm with no area penalty.