An 11b 70-MHz 1.2-mm{sup}2 49-mW 0.18-μm CMOS ADC With On-Chip Current/Voltage References

摘要

This work proposes an 11b 70-MHz CMOS pipelined analog-digital converter (ADC) as one of core circuit blocks for very high speed digital subscriber line system applications. The proposed ADC for the internal use has the strictly limited number of externally connected I/O pins while the ADC employs on-chip CMOS current/voltage references and a merged-capacitor switching technique to improve ADC performances. The ADC implemented in a 0.18-μm 1P4M CMOS technology shows the maximum signal-to-noise distortion ratio (SNDR) of 60 dB at 70 MSample/s. The ADC maintains the SNDR of 58 dB and the spurious-free dynamic resistance of 68 dB for input frequencies up to the Nyquist rate at 60 MSample/s. The measured differential and integral nonlinearities of the ADC are within ±0.63 and ±1.21 LSB, respectively. The active chip area is 1.2 mm{sup}2 and the ADC consumes 49 mW at 70 MSample/s at 1.8 V.