Hardware/software organization of a high-performance ATM host interface

摘要

A successful hardware/software architecture that resolves performance bottlenecks at the workstation-to-network host interface and offers high end-to-end performance is described. The solution reported carefully splits protocol processing functions into hardware and software implementations. The interface hardware is highly parallel and performs all per-cell functions with dedicated logic to maximize performance. Software provides support for the transfer of data between the interface and application memory, as well as the state management necessary for virtual circuit setup and maintenance. In addition, all higher-level protocol processing is implemented with host software. The prototype connects a RISC System/6000 to a SONET-based asynchronous transfer model (ATM) network carrying data at the OC-3c rate of 155 Mb/s. An experimental evaluation of the interface hardware and software has been performed. Several conclusions are drawn about this host interface architecture and the workstations to which it is connected.