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A Low-Latency List Successive-Cancellation Decoding Implementation for Polar Codes

机译:极性码的低延迟列表连续取消解码实现

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Due to their provably capacity-achieving performance, polar codes have attracted a lot of research interest recently. For a good error-correcting performance, list successive-cancellation decoding (LSCD) with large list size is used to decode polar codes. However, as the complexity and delay of the list management operation rapidly increase with the list size, the overall latency of LSCD becomes large and limits the applicability of polar codes in high-throughput and latency-sensitive applications. Therefore, in this work, the low-latency implementation for LSCD with large list size is studied. Specifically, at the system level, a selective expansion method is proposed such that some of the reliable bits are not expanded to reduce the computation and latency. At the algorithmic level, a double thresholding scheme is proposed as a fast approximate-sorting method for the list management operation to reduce the LSCD latency for large list size. A VLSI architecture of the LSCD implementing the selective expansion and double thresholding scheme is then developed, and implemented using a UMC 90 nm CMOS technology. Experimental results show that, even for a large list size of 16, the proposed LSCD achieves a decoding throughput of 460 Mbps at a clock frequency of 658 MHz.
机译:由于其可证明的容量实现性能,极地代码最近引起了很多研究兴趣。为了获得良好的纠错性能,使用具有较大列表大小的列表连续取消解码(LSCD)来解码极性代码。但是,随着列表管理操作的复杂性和延迟随着列表大小的增加而迅速增加,LSCD的总体延迟变得很大,并限制了极码在高吞吐量和对延迟敏感的应用程序中的适用性。因此,在这项工作中,研究了具有较大列表大小的LSCD的低延迟实现。具体而言,在系统级别上,提出了一种选择性扩展方法,以便不扩展某些可靠位以减少计算量和延迟。在算法级别,提出了一种双阈值方案作为列表管理操作的快速近似排序方法,以减少大列表大小的LSCD延迟。然后开发了实现选择性扩展和双阈值方案的LSCD的VLSI架构,并使用UMC 90 nm CMOS技术实现了该架构。实验结果表明,即使对于16的大列表大小,建议的LSCD在658 MHz的时钟频率下也可实现460 Mbps的解码吞吐量。

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