Design and analysis of a 0.6 V-operating merged CMOS-bipolar SRAMcell

摘要

A novel CMOS-bipolar SRAM cell has been analysed for a supplynvoltage of 0.6 V. It incorporates cross-coupled CMOS and complementarynbipolar inverters with two NMOS access transistors. Standard double-endnwrite operation with single-end read operation from the bipolar node isndiscussed. A column circuitry to accompany the cell is also proposed.nSimulation results using a standard 1.5 Μm CMOS technology show annaccess time of 5-7 ns with very low standby and active power dissipationnof 18 nW/bit and 2.2 ΜW/bit, respectively. The cell area is found tonbe less than that of the corresponding full-CMOS SRAM cell