Design assistant approach to analogue layout generation

摘要

The authors describe a novel analogue layout design assistant ALDAnbuilt around an industry-standard commercial CAD framework (CADENCE).nThe framework is used for the management of the design data and tonprovide access to low-level tools for tasks such as routing andncompaction. This approach enables effort to be concentrated on thencontrol of these tools and on addressing the specific issues andnproblems related to analogue layout. The approach adopted in ALDAninvolves a floorplanning phase, followed by a detailed physical assemblynphase. The floorplan is hierarchical and is driven by constraintsnspecified by the user; the placement within each hierarchical group isnbased on an objective function reflecting both interconnect efficiencynand silicon usage. Physical assembly is carried out in a nested,nbottom-up, sequence of place-route-compact operations, following thenhierarchical floorplan structure. ALDA achieves this by defining anplacement in the framework's layout database and then controlling thenframework's router and compactor to generate the detailed layout of eachngroup in the hierarchy. ALDA's operation is illustrated with the designnof a 61 component CMOS op-amp, which is representative of a typicalnindustrial design