Reduced complexity 1-bit high-order digital delta-sigma modulator for low-voltage fractional-N frequency synthesis applications

摘要

A reduced complexity third-order digital delta-sigma modulator for fractional-N frequency synthesis is presented. The high-performance modulator, which consists of two subblocks, has a single-bit output making it best for this sort of application. A good shaping of quantisation noise is achieved using a new architecture for a digital third-order delta-sigma modulator. The hardware required for this modulator is considerably less than that in previously reported leading to lower power and area consumption and a higher operating frequency. The field programmable gate array (FPGA) implementation of the whole system shows an SNR of at least 94 dB and an operating input range of 0.7 of the full scale (0.7 FS) with an oversampling ratio of 167. The post-layout simulation of the digital circuit using 0.25 (mu)m CMOS technology predicts a maximum operating frequency of over 60 MHz at a supply voltage of 1.5 V.