Fault characterisation and testability issues of complementary pass transistor logic circuits

摘要

Testability of basic and complex logic gates employing complementary pass transistor logic (CPL) circuits under various single stuck faults has been investigated. Results show that all stuck-on faults, bridging faults and more than 90percent of stuck-at faults in basic CPL gates are detectable only by current monitoring, generally known as I_(DDQ) testing. It is also shown that all stuck-open faults in the basic CPL gates are detectable only by logic monitoring using an appropriate two-pattern test. Testability analysis of a CPL full-adder under a single stuck-on fault condition shows that stuck-on faults on all MOS transistors of the SUM logic and the CARRY logic circuit can be detected by signal source current monitoring with appropriate test vectors. Similarly, stuck-at faults on all MOS transistors of the full-adder can be detected by current monitoring only, and stuck-open faults on all MOS transistors of the full-adder can be detected by an appropriate two-pattern test. It is concluded that signal source current monitoring (I_(DDQ) testing) is the best method for fault detection in CPL circuits, and gives more than 94percent fault coverage of stuck-at, stuck-on and bridging faults; and logic monitoring gives 100percent fault coverage of stuck-open faults.