Low power high-speed CMOS dual-modulus prescaler design with imbalanced phase-switching technique

摘要

A novel imbalanced phase-switching technique for high-speed prescaler design is investigated. Different from the traditional 50% duty cycle phase-switching technique, it uses 1/4 duty cycle phases to increase the delay budget in dual-modulus control. It significantly improves the performance of the prescaler in terms of operating frequency and power consumption, compared with the existing 50% duty cycle phase switching technique. This improvement makes it applicable to ultra-high-speed CMOS prescaler design. Two prescalers, with 2-to-1 and 4-to-1 phase switching are designed using this technique. The proposed 2-to-1 phase switching divide-by-7/8 prescaler with simplified topology using the Chartered 0.18 micron CMOS process is capable of operating from 1.5 GHz to 6 GHz with a 7 mW power consumption from a 1.8 V supply. Such operating frequency ranges cover most of the wireless LAN standards. The prescaler with 4-to-1 phase switching can work from 2 GHz to 10 GHz with a power consumption of 15 mW from a 1.8 V supply. The proposed technique is promising in relation to multi-GHz CMOS prescaler design because it eliminates the design trade-offs associated with other techniques.