Keeping Up With PCIe 3.0 Test Requirements

摘要

With the release of new and improved specifications for SATA, USB, and now PCI Express (PCIe), the era of third-generation (Gen3) serial data has arrived. Not only are the new specifications faster, they also push the limits of what is possible within the constraint of backward compatibility and high-volume manufacturing materials and tolerances such as FR4 boards, connectors, and backplanes. With each of the Gen 3 standards comes new design and test challenges, and PCIe 3.0 is no exception. While test complexity always increases with each generation, Gen 3 serial standards are changing the game with more involved compliance tests, new equalization schemes, de-embedding, and required receiver characterization tests. Troubleshooting and debugging also are more demanding with higher speeds leading to greater sensitivity to jitter and other noise. PCIe 3.0 Overview PCIe 3.0 is the next evolution of the ubiquitous and general-purpose PCIe I/O standard. At an 8-GT/s transfer rate, the interconnect performance bandwidth is doubled over PCIe 2.0 while preserving compatibility with software and mechanical interfaces. The PCI-SIG released the final PCIe 3.0 specification on Nov. 17, 2010. Motherboards and graphic cards with a modest level of PCIe 3.0 support, or at least compatibility, are appearing with higher volume. General adoption is expected toward the end of the year and mainstream adoption further into 2012.