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Power sequencing verification for FPGAs, CPUs and DSPs

机译:FPGA,CPU和DSP的电源排序验证

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摘要

Components such as FPGAs, CPUs and DSPs usually must meet very specific requirements relating to the order in which their supply voltages are powered - a process known as power sequencing. There's a power-up sequence and its reverse, the power-down sequence (also a recommended process, although not always!).During circuit design, it is important to account for the characteristics of multiple voltages for these devices during power-up and power-down, as well as during voltage interruptions. Done in the wrong order, powering up/down of voltages could lead to component damage. In addition, voltages must not exceed manufacturer-specified tolerances and, in many cases, must also comply with defined slew rates, specific delays upon reaching a target value and ramp-up times.
机译:诸如FPGA,CPU和DSP之类的组件通常必须满足与其电源电压的功率顺序有关的非常具体的要求 - 称为电源测序的过程。有一个上电序列及其反向,断电序列(也是推荐的过程,虽然并非总是!)。在电路设计期间,对于在上电时,对于这些设备的多个电压的特性是重要的断电,以及在电压中断期间。以错误的顺序完成,电压上/下电源可能导致组件损坏。此外,电压不得超过制造商指定的公差,并且在许多情况下,还必须符合定义的转换速率,在达到目标值和增速时间时特定的延迟。

著录项

  • 来源
    《Electronics world》 |2020年第2000期|18-20|共3页
  • 作者

    Tim Paasch-Colberg;

  • 作者单位
  • 收录信息 美国《科学引文索引》(SCI);美国《工程索引》(EI);
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类
  • 关键词

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