A low power dissipation architecture of high-performance multiprocessor for state-space digital filters using block-state realization

摘要

In this paper, a low power dissipation architecture of high-performance multiprocessor is proposed for state- space digital filters using block-state realization in order to realize high-accuracy, high-speed process with reduced hardware previously proposed by the authors. Distributed arithmetic is applied to this high-performance VLSI proc- essor so that a high sampling rate can be maintained even at a higher-order filter. Further, in proposed method, the function generation of the distributed arithmetic carried out previously by ROM is now realized with the optimum function circuit using logic gates.