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首页> 外文期刊>IEEE Transactions on Electron Devices >Characterization of Fast Relaxation During BTI Stress in Conventional and Advanced CMOS Devices With $hbox{HfO}_{2}/hbox{TiN}$ Gate Stacks
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Characterization of Fast Relaxation During BTI Stress in Conventional and Advanced CMOS Devices With $hbox{HfO}_{2}/hbox{TiN}$ Gate Stacks

机译:具有$ hbox {HfO} _ {2} / hbox {TiN} $门堆叠的传统和高级CMOS器件在BTI应力期间快速弛豫的特性

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摘要

We evaluate the performance of a novel fast characterization methodology for NBTI and PBTI measurements. We show that the use of a programmable PCI card in combination with linear current amplifiers provides the following means: (a) to perform short BTI stresses down to ~ 30 mus; (b) to perform fast sensing with delay times tdelay ~ 30 mus and a voltage resolution of ~ 1 mV; and (c) to use arbitrary programmable stress-and-sense sequences covering many decades in time. We used the fast PCI card-based measurement system for fast NBTI-relaxation measurements in SiON/poly-Si gate stacks, as well as for a systematic study of PBTI relaxation with HfO2/ TiN gate stacks. We show for the first time that the Vt relaxation after PBT stress in nFETS with HfO2/TiN gate stacks and the Vt relaxation after NBT stress in pFETs with SiON/poly-Si gate stacks exhibit strong similarities: We found the time dependence of both types of relaxation to exhibit to first order a log(t) dependence over seven orders of magnitude in time, suggesting that both phenomena are governed by charge removal by tunneling and that tunneling front-based modeling may be used to quantify the observations.
机译:我们评估NBTI和PBTI测量的新型快速表征方法的性能。我们表明,将可编程PCI卡与线性电流放大器结合使用可提供以下方法:(a)执行短至约30 mus的短BTI应力; (b)以延迟时间tdelay〜30 mus和电压分辨率〜1 mV进行快速感测; (c)使用涵盖数十年时间的任意可编程压力和感觉序列。我们将基于PCI卡的快速测量系统用于SiON /多晶硅栅叠层中的快速NBTI松弛测量,以及对HfO2 / TiN栅叠层中PBTI弛豫的系统研究。我们首次展示了在具有HfO2 / TiN栅堆叠的nFET中,PBT应力后的Vt弛豫与在具有SiON /多晶硅栅堆叠的pFET中的NBT应力后的Vt弛豫具有很强的相似性:我们发现两种类型的时间依赖性弛豫时间在七个数量级上表现出一阶log(t)依赖关系,这表明这两种现象都由隧穿电荷清除控制,并且基于隧穿前沿的建模可用于量化观测值。

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