TCAD-Based Investigation of Statistical Variability Immunity in U-Channel FDSOI n-MOSFET for Sub-7-nm Technology

摘要

In this article, the impact of random fluctuation sources, such as metal gate granularity (MGG), line edge roughness (LER), and random dopant fluctuations (RDFs), are numerically studied forU-shapedn-channel fully depleted silicon on insulator (FDSOI) MOSFET (U-SOIFET) over conventionaln-channel FDSOIMOSFET (C-SOIFET) for 7-nm technology node. This article reports that improved short-channel effect immunity in U-SOIFET results in less 1 sigma threshold voltage (V-T) and ON-current (I-ON) fluctuations compared to C-SOIFET due to MGG and LER variability sources. U-SOIFET exhibits a low V-T mismatch index (A(Delta VT) = 1.78mV.mu m) close to the literature reported. Due to combined variability sources, U- SOIFET shows less V-T, I-ON, subthreshold swing (SS), and DIBL fluctuations compared to C-SOIFET. Immunity to statistical variability sources makes U-SOIFET a suitable silicon on insulator (SOI) device architecture for future CMOS logic device applications.