...
首页> 外文期刊>IEEE Electron Device Letters >Impacts of Gate Electrode Materials on Threshold Voltage (V{sub}(th)) Instability in nMOS HfO{sub}2 Gate Stacks Under DC and AC Stressing
【24h】

Impacts of Gate Electrode Materials on Threshold Voltage (V{sub}(th)) Instability in nMOS HfO{sub}2 Gate Stacks Under DC and AC Stressing

机译:栅电极材料对直流和交流应力下nMOS HfO {sub} 2栅堆叠中阈值电压(V {sub}(th))不稳定性的影响

获取原文
获取原文并翻译 | 示例
           

摘要

Ultrathin nMOSFET hafnium oxide (HfO2) gate stacks with TiN metal gate and poly-Si gate electrodes are compared to study the impact of the gate electrode on long term threshold instability reliability for both dc and ac stress conditions. The poly-Si/high-k interface exhibits more traps due to interfacial reaction than the TiN/high-K interface, resulting in significantly worse dc V{sub}(th) instability. However, the V{sub}(th) instability difference between these two stacks decreases and eventually diminishes as ac stress frequency increases, which suggests the top interface plays a minor role in charge trapping at high operating frequency. In addition, ac stress induced interface states (Nit) can be effectively recovered, resulting in negligible G{sub}m degradation.
机译:比较了具有TiN金属栅极和多晶硅栅极的超薄nMOSFET氧化ha(HfO2)栅极叠层,以研究栅极对直流和交流应力条件下长期阈值不稳定性可靠性的影响。与TiN / high-K界面相比,由于界面反应,poly-Si / high-k界面显示出更多的陷阱,从而导致dc V {sub}(th)不稳定。但是,这两个堆栈之间的V {sub}(th)不稳定性差减小,并随着交流应力频率的增加而最终减小,这表明顶部界面在高工作频率下的电荷捕获中起着较小的作用。此外,可以有效地恢复交流应力引起的界面态(Nit),从而导致G {sub} m的降低可忽略不计。

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号