...
首页> 外文期刊>IEEE Electron Device Letters >Heterostructure Barriers in Wrap Gated Nanowire FETs
【24h】

Heterostructure Barriers in Wrap Gated Nanowire FETs

机译:包裹门控纳米线FET中的异质结构壁垒

获取原文
获取原文并翻译 | 示例
           

摘要

We present results on the effects of inserting a heterostructure barrier along the channel of vertical wrapped insulator-gate field-effect transistors (WIGFETs). Two sets of devices were fabricated, one InAs WIGFET and one with a 50-nm-long $hbox{InAs}_{0.8}hbox{P}_{0.2}$ segment in the channel. This addition of P induces a barrier in the conduction band of 130 mV, measured from the Fermi-level. The barrier blocks the diffusion current through the channel and reduces the feedback gating of holes created from band-to-band tunneling, resulting in improvements in on/off current ratio, and subthreshold characteristics. The heterosegment also induces a shift in the threshold voltage and provides an additional parameter for threshold voltage control in nanowire III–V MOSFETs.
机译:我们目前的结果是沿着垂直包裹的绝缘体栅场效应晶体管(WIGFET)的沟道沿沟道插入异质结构势垒。制造了两组器件,一组是InAs WIGFET,另一组是在通道中具有50纳米长的$ hbox {InAs} _ {0.8} hbox {P} _ {0.2} $段。从费米能级测得,P的这种引入在130 mV的导带中感应出势垒。势垒阻挡了通过沟道的扩散电流,并减少了由带间隧穿产生的空穴的反馈门控,从而改善了开/关电流比和亚阈值特性。异质段还会引起阈值电压的漂移,并为纳米线III–V MOSFET中的阈值电压控制提供附加参数。

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号