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首页> 外文期刊>Advanced Research in Electrical and Electronic Engineering: AREEE >A Method for Improving the Settling Time of Phase-locked loop during Acquisition for Communication Systems
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A Method for Improving the Settling Time of Phase-locked loop during Acquisition for Communication Systems

机译:一种改进通信系统采集期间锁相环沉降时间的方法

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This paper describes a novel method for proportional- integral-derivative controlled phase-locked loop model for communication system for better settling time during acquisition. A proportional-integral-derivative controlled block is inserted in place of a 4" order loop filter of the phase-locked loop. The s-domain transfer function of the system is derived for linear analysis. The settling, phase margin, bandwidth and stability of the system are analyzed through behavioral simulation by using MATLAB platform. It is observed that the proportional-integral-derivative controlled phase-locked loop model reduces the settling time (~ nS) in comparison to phase-locked loop with 4" order loop filter in the loop (~uS).
机译:本文介绍了用于通信系统的比例 - 积分衍生物控制锁相模型的新方法,以便在采集期间更好地稳定时间。 插入比例积分控制块代替锁相环的4“阶环路滤波器。导出系统的S域传递函数以进行线性分析。沉降,相位裕度,带宽和稳定性 通过使用MATLAB平台通过行为仿真分析系统。观察到比较 - 积分 - 导数控制的锁相循环循环模型与具有4“顺序环路滤波器的锁相环相比减少了稳定时间(〜ns) 在循环中(〜美国)。

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