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Design and Implementation of Quad-Site Testing on FPGA Platform

机译:FPGA平台上的四网站测试的设计与实现

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As manufacturing efficiency has become a main focus of today’s business, it is very critical to surge the throughput by developing different test strategies. With throughput, testing cost also has been recognized as the major challenge in the future of leading semiconductors. Reducing test time is a significant effort to maximize throughput as the complexity increases in future generation outcomes and devices. So, low-cost Automatic Test Equipment (ATE) with parallel test can be promoted as the obvious solution for challenges said above. In parallel testing, multiple devices-under-test (DUT) can be tested at a time that enhances way of testing by increasing product flow, limiting gross test times, and efficient usage of tester. The proposed Integrated Circuit (IC) tester is used to implement multi-site testing (Quad-Site testing) and concurrent testing. It exhibits multi-site efficiency which substantially enhances the throughput by reducing test time. Modular, re-configurable test system provides cost-saving solution. To confirm these effects, authors have presented experimental results for Quad site testing of different ICs namely Decoder, Buffer, Multiplexer and Logic gates. This portable IC Tester handles variety of IC packages like Dual Inline Package (DIP), Small Outline Integrated Circuit (SOIC), Thin Shrink Small Outline Package (TSSOP). With functional test, the proposed tester also verified the AC Parametric tests (i) Propagation Delay is 20ns (ii) Operating frequency with 50MHz for Decoder IC (74HC138). The proposed IC tester consumes 70% less power and throughput enhanced by 11% compared to existing IC testers.
机译:由于制造效率已成为当今业务的主要重点,通过开发不同的测试策略来激增吞吐量是非常重要的。通过吞吐量,测试成本也被认为是未来领先半导体的主要挑战。减少测试时间是最大限度地努力,以使吞吐量最大化,因为未来一代成果和设备的复杂性增加。因此,可以促进具有并行测试的低成本自动测试设备(ATE)作为上述挑战的明显解决方案。在并行测试中,可以在通过增加产品流量,限制总测试时间和测试仪的有效使用,这是一次测试多种测试的测试(DUT)。所提出的集成电路(IC)测试仪用于实现多站点测试(四端站测试)和并发测试。它表现出多网站效率,通过降低测试时间,大大提高了吞吐量。模块化可重新配置测试系统提供节省成本的解决方案。为了确认这些效果,作者提出了对不同IC的四网站测试的实验结果,即解码器,缓冲区,多路复用器和逻辑门。该便携式IC测试仪处理各种IC封装,如双线式包装(DIP),小型轮廓集成电路(SOIC),细长的缩小小纲包(TSSOP)。通过功能测试,所提出的测试仪还验证了AC参数测试(I)传播延迟是20ns(ii)的运行频率,用于解码器IC(74HC138)的50MHz。与现有IC测试仪相比,建议的IC测试仪消耗了70%的电力和吞吐量增强了11%。

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