FPGA Based Decimal Matrix Code for Passive RFID Tag

摘要

In this paper, Decimal Matrix Code is developed for RFID passive tag. The proposed DMC uses the decimal algorithm to obtain the maximum error detection and correction capability. The Encoder-Reuse Technique is used to minimize the area overhead of extra circuits without disturbing the complete encoding and decoding processes. ERT uses DMC encoder itself to be part of the decoder. The Simulation results reveals that the Decimal Matrix Code is effective than existing Matrix and Hamming odes in terms of Error Correction Capability. Xilinx ISE 14.7 Software is used for the simulation outputs. The complete design is verified and tested on Spartan-6 FPGA board. The performance of system is measured in terms of power, area and delay. The Synthesis result shows that, the power required for complete design of Decimal Matrix Code is 0.1mW with a delay of 3.109ns.