Design of CMOS PSCD Circuits and Checkers forStuck-At and Stuck-On Faults

摘要

We present in this paper an approach to designing partially strongly code-disjoint(PSCD) CMOS circuits and checkers, considering transistor stuck-on faults in additionto gate-level stuck-at faults. Our design-for-testability (DFT) technique requires only asmall number of extra transistors for monitoring abnormal static currents, coupled witha simple clocking scheme, to detect the stuck-on faults concurrently. The DFT circuitrynot only can detect the faults in the functional circuit but also can detect or tolerate faultsin itself, making it a good candidate for checker design. Switch and circuit levelsimulations were performed on a sample circuit, and a sample 4-out-of-8 code checkerchip using the proposed technique has been designed, fabricated, and tested, showing thecorrectness of the method. Performance penalty is reduced by a novel BiCMOS checkercircuit.