STT-RAM Based Energy-Efficient Hybrid Cache Architecture for 3D Chip Multiprocessors

摘要

With increasing the number of cores on a chip in Chip-Multiprocessors (CMPs), more cache resources are needed, and as a result, the leakage power consumption of the cache accounts for a larger proportion of the total chip power consumption. The emerging non-volatile memory (NVM) is expected to replace traditional memory devices due to its high density, near zero leakage power, and nonvolatility. In this paper, we use STT-RAM, a most promising candidate of NVM, to construct a energy-efficient hybrid cache architecture for 3D CMP. For the hybrid cache architecture design, we proposed a spherical placement approach to determine the optimal placement of STT-RAM and SRAM cache banks. This paper further proposes an optimized hybrid cache dynamic migration scheme, to reduce the data migration jitter and solve the problem of data migration failure in the hybrid cache architecture. The experimental results show that our proposed hybrid cache architecture with spherical placement and optimized data migration scheme can achieve 34.94% energy saving on average with only 1.49% performance degradation, compared with the architecture which uses pure SRAM as the cache in the same capacity.