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首页> 外文期刊>International journal of reconfigurable computing >An Evaluation of an Integrated On-Chip/Off-Chip Network forHigh-Performance Reconfigurable Computing
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An Evaluation of an Integrated On-Chip/Off-Chip Network forHigh-Performance Reconfigurable Computing

机译:高性能可重构计算的片上/片外集成网络评估

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As the number of cores per discrete integratedcircuit (IC) device grows, the importance of the network on chip (NoC) increases. However, the body of research inthis area has focused on discrete IC devices alone whichmay or may not serve the high-performance computingcommunity which needs to assemble many of these devicesinto very large scale, parallel computing machines. This paperdescribes an integrated on-chip/off-chip network that hasbeen implemented on an all-FPGA computing cluster. Thesystem supports MPI-style point-to-point messages, collectives,and other novel communication. Results include the resourceutilization and performance (in latency and bandwidth).
机译:随着每个分立集成电路(IC)设备的内核数量的增加,片上网络(NoC)的重要性也在增加。但是,该领域的研究重点仅集中在分立的IC设备上,这些设备可能会或可能不会服务于高性能计算社区,而高性能计算社区需要将许多此类设备组装成超大型并行计算机。本文描述了已在全FPGA计算集群上实现的集成片上/片外网络。该系统支持MPI样式的点对点消息,集合和其他新颖的通信。结果包括资源利用率和性能(在延迟和带宽方面)。

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