Power Efficient Probabilistic Multiplier for Digital Image Processing Subsystems

摘要

Power efficient is an important availability for various image processing subsystems and portable devices applications. The design of proposed probabilistic multiplier is to trade a lesser amount of accuracy with reduced power consumption. In this paper, the probabilistic multiplier is eliminating the some part of the partial product generating path in least significant bit to reduce the power consumption and transistor count. The power consumption and probabilistic error behaviour of the proposed multiplier is verified and compared with other multipliers.