Hardware Implementation of PAPR Reduction with Clipping and Filtering Technique for Mobile Applications

摘要

Orthogonal frequency division multiplexing (OFDM) is preferred for mobile communicationsapplications due to its increased data transmission capability. At one hand, it has advantages of beingrobust to multipath fading and possessing high data rate transmission capability, on the other hand itsuffers from high peak to average power ratio (PAPR). In this paper FPGA implementation of clippingand filtering method have been implemented on Xilinx Spartan 3 Protoboard XC 3S 400 board for 4QAM OFDM signals. The results obtained have been compared with National Instrument’s (NI) AWRvisual system simulator and Matlab software simulations. FPGA implementation of pre-filtering and postclipping technique results with 2.2 dB PAPR, whereas, PAPR values obtained in the case of pre-clippingand post filtering method, are 10.6, 10.7 and 10.9 dB with NI’s AWR simulation, Matlab simulation andFPGA implementation respectively. When compared with original OFDM signal having 12.5 dB PAPR,FPGA implementation of pre-filtering and post-clipping reduces PAPR by 10.3 dB, whereas for the caseof pre-clipping and post-filtering technique the reductions in PAPR are 1.6, 1.8 and 1.9 dB with FPGAimplementation, Matlab and NI’s AWR software simulations respectively.