A Hardware Implementation of Hybrid Image Compression

摘要

Digital image processing is a method for processing digital images. Images are represented in various forms by using Image Transforms. Image transformation is carried out by applying mathematical operations on an image. There are various transform methods available such as Discrete Wavelet Transform (DWT), Discrete Cosine Transform (DCT), Karhunen–Loeve Transform (KLT), etc. These transformation methods find application in compression, enhancement, feature extraction, and pattern recognition etc. DWT is a wavelet transformation from spatial to frequency domain where the wavelets are discretely sampled. The main advantage of DWT is that the image can be represented in multi resolution form. Advantages of DWT are that it provides a high compression ratio by avoiding the blocking artefacts, provides better localization in spatial and frequency domains. But there is a great need to improve the throughput and overall design cycle time. In this paper, new hybrid architecture is proposed for image compression. The proposed hybrid architecture is a combination of DWT and DCT methods. The architecture is designed by using Verilog HDL and is synthesized by using Xilinx ISE 14.2 Version. The architecture is targeted on Spartan 6 FPGA board. The standard Lena image [512x512] is used as a test image. A comparison of encoding time is made between standalone DWT and hybrid DWT-DCT proposed method. The results show that the encoding time of proposed hybrid [DWT-DCT] image compression method is faster than the standalone DWT method.