The design of Networks-on-Chip (NoCs) involves several key issues, including the topological mapping, that is, the mapping of the processing elements or Intellectual Properties (IPs) to the network nodes. Although several proposals have been focused on topological mapping last years, this topic is still an open issue. In this paper, we propose, in an extended manner, a topology-independent mapping technique for application-specific NoCs that can be used with regular or irregular topologies, and with any routing algorithm. This technique globally matches the communication pattern generated by the IPs with the available network bandwidth in the different parts of the network. The evaluation results show that the proposed technique can provide better performance than other mapping techniques not only in terms of average latency and network throughput, but also in terms of power consumption.
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