Hardware Accelerators for Elliptic Curve Cryptography

摘要

In this paper we explore different hardware accelerators for cryptography based on ellipticcurves. Furthermore, we present a hierarchical multiprocessor system-on-chip (MPSoC) platformthat can be used for fast integration and evaluation of novel hardware accelerators. In respectof two application scenarios the hardware accelerators are coupled at different hierarchy levelsof the MPSoC platform. The whole system is implemented in a state of the art 65 nm standard celltechnology. Moreover, an FPGA-based rapid prototyping system for fast system verification ispresented. Finally, a metric to analyze the resource efficiency by means of chip area, executiontime and energy consumption is introduced.