High Performance Spin-Orbit-Torque (SOT) Based Non-volatile Standard Cell for Hybrid CMOS/Magnetic ICs

摘要

Spin-orbit-torque magnetic tunnel junction (SOT-MTJ) is an emergent spintronics device with a promising potential. It resolves many issues encountered in the current MTJs state of the art. Although the existing Spin Transfer Torque (STT) technology is advantageous in terms of scalability and writing current, it suffers from the lack of reliability because of the common write and read path which enhances the stress on the MTJ barrier. Thanks to the three terminal architecture of the SOT-MTJ, the reliability is increased by separating the read and the write paths. Moreover, SOT-induced magnetization switching is symmetrical and very fast. Thus, doors are opened for non-volatile and ultra-fast Integrated Circuits (ICs). In this paper, we present the architecture of a mixed CMOS/Magnetic non-volatile flip-flop (NVFF). We use a compact model of the SOT device developed in Verilog-A language to electrically simulate its behaviour and evaluate its performances. The designed standard cell offers the possibility to use the usual CMOS flip-flop functionality. In addition, it enables storing and restoring the magnetic data by exploiting the non-volatility asset of MTJs when the circuit is powered off. With a 28nm dimension, the SOT-MTJ based NVFF demonstrated a very high speed switching (hundreds of picoseconds) with 7× decrease in term of writing energy when compared to the STT device.