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Configurable and scalable class of high performance hardware accelerators for simultaneous DNA sequence alignment

机译:可配置和可扩展的高性能硬件加速器,用于同时进行DNA序列比对

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A new class of efficient and flexible hardware accelerators for DNA local sequence alignment based on the widely used Smith-Waterman algorithm is proposed in this paper. This new class of accelerating structures exploits an innovative technique that tracks the origin coordinates of the best alignment to allow a significant reduction of the size of the dynamic programming matrix that needs to be recomputed during the subsequent traceback phase, providing a considerable reduction of the resulting time and memory requirements. The significant performance of the enhanced class of accelerators is attained by also providing support for an additional level of parallelism: the capability to concurrently align several query sequences with one or more reference sequences, according to the specific application requisites. Moreover, the accelerator class also includes specially designed processing elements that improve the resource usage when implemented in a Field Programmable Gate Array (FPGA), and easily provide several different configurations in an Application Specific Integrated Circuit (ASIC) implementation. Obtained results demonstrated that speedups as high as 278 can be obtained in ASIC accelerating structures. A FPGA-based prototyping platform, operating at a 40 times lower clock frequency and incorporating a complete alignment embedded system, still provides significant speedups as high as 27, compared with a pure software implementation.
机译:提出了一种基于广泛使用的Smith-Waterman算法的新型高效灵活的DNA局部序列比对硬件加速器。这类新型的加速结构采用了一种创新技术,该技术可跟踪最佳对齐方式的原点坐标,从而显着减小了动态编程矩阵的大小,该矩阵在后续的追溯阶段需要重新计算,从而显着减少了结果时间和记忆要求。增强的加速器类别的显着性能还通过提供对更高级别的并行性的支持来实现:根据特定的应用程序要求,可以同时将多个查询序列与一个或多个参考序列对齐。此外,加速器类还包括经过特殊设计的处理元件,这些处理元件在现场可编程门阵列(FPGA)中实现时可改善资源使用,并在专用集成电路(ASIC)实现中轻松提供几种不同的配置。获得的结果表明,在ASIC加速结构中可以获得高达278的加速。与纯软件实现相比,基于FPGA的原型平台可在低40倍的时钟频率下运行,并集成了完整的对准嵌入式系统,仍可提供高达27倍的显着提速。

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