Instruction scheduling and transformation for a VLIW unified reduced instruction set computer/digital signal processor processor with shared register architecture

摘要

The popularity of multimedia applications made them a major theme in embedded systems. The keyrncomponent for supporting multimedia application well is embedded processor. Thus, we have designed andrnimplemented an embedded processor, called UniDual processor, to achieve this objective. Its key featuresrnare the integration of instructions of reduced instruction set computers (RISCs) and digital signal processorsrn(DSPs) as well as the support of special instruction set and shared-based clustered register architecture.rnHowever, an important issue of UniDual that remains open is how to efficiently allocate registers.rnIn this paper, we present a scheduling and instruction transformation approach to resolve the aforementionedrnissue. The proposed approach schedules instructions and then transforms overlapped instructionsrninto RISC and DSP instructions by taking communication overhead and hardware limitations intornaccount. Compared with the greedy approach, the evaluation shows that our work is relatively effective inrnperformance and code size reduction.