Methodology to verify, debug and evaluate performances of NoC based interconnects

摘要

The authors of this paper introduce some verification issues regarding systems on chip (SoC) structures and transfer protocols, and further introduce some of the means available to achieve network on chip (NoC) design correctness and automate verification, involving in vitro diagnostics (IVD), interactive whiteboard (IWB), and root cause analysis (RCA) tools and methods. The main contributions in this paper are the IVD that can flexibly interconnect verification intellectual properties (VIPs) and support coverage collection and the IWB to allow automation and creation of needed environments.