Modular vector processor architecture targeting at data-level parallelism

摘要

This research presents a VHSIC hardware description language (VHDL) vector processor architecture specifically designed to address data-level parallelism by separating the vector lanes to use its own private memory, avoiding any stalls during memory access instructions. Several vector processors have been developed to date, and some are even targeted for specific applications, such as matrix multiplication. This particular research would be a target for an application like the fast Fourier transform (FFT), which requires data shuffling. This architecture addresses the vector processors' slow memory accesses, which are not addressed by prior research in vector processors; the data shuffle instructions are supported by a shuffle engine in each lane, which is placed after the lane's local memory, connected to the common bus.