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首页> 外文期刊>Computers & Digital Techniques, IET >Radix-43 based two-dimensional FFT architecture with efficient data reordering scheme
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Radix-43 based two-dimensional FFT architecture with efficient data reordering scheme

机译:基于RADIX-4 3 具有高效数据重新排序方案的二维FFT架构

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摘要

Multi-dimensional Discrete Fourier Transforms (DFTs) play an important role in signal and image processing applications. Image reconstruction is a key component in signal processing applications like medical imaging, computer vision, face recognition etc. Two dimensional fast Fourier Transform (2D FFT) and Inverse FFT plays vital role in reconstruction. In this paper we present a fast 64 x 64 point 2D FFT architecture based on radix-43 algorithm using a parallel unrolled radix-4(3) FFT as the basic block. Our radix-4(3) architecture is a memory optimized parallel architecture which computes 64-point FFT, with least execution time. Proposed architecture produces reordered output of both 64-point one dimensional (1D) FFT and 64 x 64 point 2D FFT, without using any additional hardware for reordering. The proposed architecture has been implemented in UMC 40nm CMOS technology with clock frequency of 500 MHz and area of 0.841 mm(2). The power consumption of proposed architecture is 358 mW at 500 MHz. Energy efficiency (FFTs computed per unit of energy) is 341 points/Joule. Computation time of 64 x 64 point FFT is 8.19 mu s. ASIC implementation results shows better performance of proposed work in terms of computation time when compared with state-of-art implementation. Proposed architecture has also been implemented in Virtex-7 FPGA which gives comparable area.
机译:多维离散傅里叶变换(DFT)在信号和图像处理应用中起重要作用。图像重建是信号处理应用中的关键组件,如医学成像,计算机视觉,面部识别等。二维快速傅里叶变换(2D FFT)和逆FFT在重建中起着重要作用。在本文中,我们使用并行展开的基数-4(3)FFT作为基本块,呈现出基于基于RADIX-43算法的快速64 x 64点2D FFT架构。我们的RADIX-4(3)架构是存储器优化并行架构,其计算64点FFT,最小执行时间。建议的架构产生重新排序的64点一维(1D)FFT和64 x 64点2D FFT,而不使用任何额外的硬件进行重新排序。该建筑造型已在UMC 40nm CMOS技术中实现,时钟频率为500MHz,面积为0.841mm(2)。建议架构的功耗为500 MHz的358兆瓦。能效(每单位能量计算的FFT)是341分/焦耳。计算时间为64 x 64点FFT为8.19 mu s。与最先进的实施相比,ASIC实现结果表明,在计算时间方面表现出提出的工作。拟议的架构也在Virtex-7 FPGA中实现,它提供了可比区域。

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