A generic, formal language-based methodology for hierarchical floorplanning-placement

摘要

Floorplanning in 2-D or 3-D space is always a difficult and time consuming problem for automated manufacturing, storaging, civil engineering design and especially for the physical layout design cycle of the chip design automation. In particular, the physical layout cycle itself consists of several steps, such as partitioning, floorplanning, placement, synthesis, routing, and compaction, where the right placement of the appropriate components is the most important element of performance. In this paper, a generic floor-planning methodology is presented by offering a good solution to such problems. The methodology is based on the hierarchical cooperation of two context-free languages (Scan and Geometria). In order to achieve an acceptable planning, the Scan language defines the partitioning of the floor area and the global acquisition strategy (scan patterns) for the placement of the macro-blocks. On the other hand, the Geometria language deals with the local synthesis of the block under the constraints superimposed by global scan patterns. The results obtained by this methodology are very promising in comparison with other floorplanning methodologies.