ASIC Verification: Integrating Formal Verification With HDL-Based Courses

摘要

The rapid progress of chip fabrication technology has paved the way to the design of complex ASICs containing several million transistors. According to published work, verification of these ASICs has emerged as a major bottleneck consuming up to three-quarters of total pre-silicon resources. This fact has tempted the scientific community to propose alternatives to the classical simulation approach. Recently, formal verification techniques have gained large attention and are becoming a key component in reducing the verification effort required to meet compressed design cycle times. In addition to the reliability factor, these techniques are proven to be cost effective since they help in reducing time allocated for test bench creation which is typically a time consuming and error prone activity. In this paper the formal or static approach is presented in a context that encourages its integration into HDL-based courses at the senior or first year graduate level. Advantages of the static approach will be discussed by presenting property formulation for selected RTL designs. Moreover, the property language Property Specification Language (PSL), IEEE standard 1850, will be used in presenting property formulations. System Verilog Assertions (SVA) is another viable option for property specification and can be readily substituted for PSL.