A folding ADC preprocessing architecture employing a robustsymmetrical number system with gray-code properties

摘要

A folding analog-to-digital converter (ADC) preprocessingnarchitecture based on a new robust symmetrical number system (RSNS) isnpresented. The RSNS preprocessing architecture is a modular scheme innwhich the integer values within each modulus (comparator states), whennconsidered together, change one at a time at the next positionn(gray-code properties). Although the observed dynamic range of the RSNSnADC is less than the optimum symmetrical number system ADC, the RSNSngray-code properties make it particularly attractive for error control.nWith the RSNS preprocessing, the encoding errors due to comparatornthresholds not being crossed simultaneously are eliminated. As a result,nthe interpolation circuits can be removed and only a small number ofncomparators are required. Computer generated data is used to helpndetermine the properties of the RSNS. These properties include thendynamic range (largest number of distinct consecutive vectors) and thenlocation of the dynamic range within the number system. Closed-formnexpressions for the dynamic range are also presented for channel modulinof the form m1=2k-1, m2=2k,nm3=2k+1. RSNS ADC circuit design principles arenpresented. To compare the advantages of the RSNS ADC with previouslynpublished results, the transfer function of a 3-channel architecturen(k=2) is evaluated numerically using SPICE