Design and implementation of a low-voltage fast-switchingmixed-signal-controlled frequency synthesizer

摘要

A new frequency synthesizer based on combining the analognphase-locked loop (PLL) and the all digital PLL (ADPLL) is presented.nThe frequency synthesizer achieves high frequency resolution, broadnfrequency range, high switching speed, and low supply voltage. Thenoscillator is controlled by both the digital control word and thencontrol voltage of the analog PLL. It is an array oscillator implementednby symmetric load differential inverting buffers which provide betternrejection to supply noise and fabrication variance. Fractional-N dividernand delay interpolation technique are employed to enhance the dividernresolution without inducing jitter. A binary search algorithm is used tonfind the proper digital frequency control word, which can be saved fornlater use and greatly speed up the frequency switching process.nFabricated using a 0.6-Μm SPTM CMOS process, the synthesizer achievesna frequency range of 54-154 MHz with a frequency error less than 1 ppmnand a frequency switching time less than 10 Μs. The chip consumesnvery little power and draws 47 mW from a 2-V supply voltage