Design and Simulation of a 12 Gb/s Transceiver With 8-Tap FFE, Offset-Compensated Samplers and Fully Adaptive 1-Tap Speculative/3-Tap DFE and Sampling Phase for MIPI A-PHY Applications

摘要

This brief presents a fully adaptive high-speed serial interface designed in 28-nm planar CMOS technology for future mobile industry processor interface (MIPI)-compliant automotive microcontrollers operating at 12 Gb/s over long-reach channels. The transmitter has a voltage-mode driver and operates at full rate featuring an 8-tap feed-forward equalizer with tap programmability of 1/16. The transmitter's output impedance tuning is performed through activation of different driver replicas. The half-rate receiver features an analog front-end which comprises a variable-gain amplifier and a continuous-time linear equalizer. The subsequent decision-feedback equalizer (DFE) has three programmable taps, the first of which is loop-unrolled to relax timing constraints. Another amplifier is embedded in the DFE's summing node. We employ transistor-level simulations to assess the capability of the interface to optimally adapt to realistic channels: the DFE taps and the data sampling phase are automatically adapted by means of a behavioural implementation of an least mean squares algorithm based on information gathered through error sampling. Such an interface was simulated on channels representing likely MIPI A-PHY to-be-defined specifications featuring up to 33 dB loss at 6 GHz.