High-level FSMD design and automated clock gating with CoDeL

摘要

A high-level VLSI design platform, called CoDeL, which allows hardware description at the algorithm level and thus dramatically reduces design time, is presented. It now directly supports the use of fixed-point operations to ease description of digital signal processing (DSP) algorithms. Also, to dramatically reduce dynamic power dissipation in the resulting architecture, it automatically inserts clock gating for registers at the behavioural level. This is believed to be the first hardware design environment that allows an algorithmic description of a component and yet produces a power-aware design. The DSPstone benchmark is used to thoroughly evaluate this fixed-point design platform for the design of power-efficient DSP architectures. Power analysis is used to compare the effectiveness of CoDeL's automated clock gating to automated clock gating using Synopsys tools. The results show that a combination of CoDeL and Synopsys clock gating provides 16% more power savings, on average, than Synopsys' automated clock gating alone. Finally, the CoDeL platform is compared to a modern DSP processor, and it is found that the CoDeL platform produces designs with somewhat slower run times, but dramatically lower power dissipation.