Data-Parallelism Based Hardware Architecture for the Intra-Coding Module Used in the H.264/AVC Encoder

著录项

• 来源
  《Arabian Journal for Science and Engineering》 |2014年第5期|3781-3797|共17页
• 作者

  Kamel Messaoudi; Salah Toumi; El-Bay Bourennane; Maamar Touiza;

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• 作者单位

  1.Electronic Department Mentouri University of Constantine Route Ain El-bay Constantine Algeria 2.LERICA Laboratory Badji Mokhtar University of Annaba Sidi Amar B.P# 12 Annaba Algeria 3.LE2I Laboratory Burgundy University BP 47 870 21078 Dijon Cedex France;

  2.LERICA Laboratory Badji Mokhtar University of Annaba Sidi Amar B.P# 12 Annaba Algeria;

  3.LE2I Laboratory Burgundy University BP 47 870 21078 Dijon Cedex France;

  3.LE2I Laboratory Burgundy University BP 47 870 21078 Dijon Cedex France;

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• 收录信息 美国《科学引文索引》(SCI);
• 原文格式 PDF
• 正文语种 eng
• 中图分类
• 关键词

  Intra-coding; H.264/AVC codec; IP encoder; Data-parallelism; FPGA;

  机译：内部编码;H.264 / AVC编解码器;IP编码器;数据并行;FPGA;