A memory window expression to evaluate the endurance of ferroelectric FETs

摘要

The recent discovery of ferroelectricity in HfO_2 has revived the interest into non-volatile memories based on ferroelectric transistors (FeFETs). The key advantages of these FeFETs include the low power consumption and the compatibility with the existing CMOS process. On the other hand, issues related mainly to endurance still represent a challenge to the development of the technology. In this Letter, we propose to exploit an analytical expression for the Memory Window (MW) as a simple yet effective characterization tool to evaluate the endurance of FeFETs. The MW is defined as the difference between threshold voltages occurring due to polarization switching. The analytical formulation of the MW allows one to quickly estimate the generated trap concentration as a function of number of writing cycles (or time) without recurring to numerical simulations. With the aid of the analytical model, we find that for typical program/erase pulse amplitudes and duration, endurance has a weak dependence on writing conditions. The characterization technique based on the MW would allow the systematic comparison of the performance and endurance of next-generation FeFETs.