Achieving low parasitic resistance in Ge p-channel metal-oxide-semiconductor field-effect transistors by ion implantation after germanidation

摘要

The parasitic resistance (R_(para)) of Ge p-channel metal-oxide-semiconductor field-effect transistors (p-MOSFETs) fabricated by ion implantation after germanidation (IAG) has been investigated by varying the drive-in annealing temperature. The lowest R_(para) of 835 Ω μm was achieved after 450 ℃ drive-in annealing for 1 min. Boron segregation between NiGe and Ge induced by drive-in annealing has advantages in forming an abrupt metallic source/drain (S/D) junction and contributes to the decrease in R_(para). The appropriate process window for fabricating Ge p-MOSFETs by IAG was also given. IAG, a pathway for introducing a Ge channel into CMOS technology beyond the 10nm node, was proved to be effective for reducing R_(para).