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Selective Growth and Contact Gap-Fill of Low Resistivity Si via Microwave Plasma-Enhanced CVD

机译:通过微波等离子体增强CVD的低电阻率Si的选择性生长和接触间隙填充

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摘要

Low resistivity polycrystalline Si could be selectively grown in the deep (~200 nm) and narrow patterns (~20 nm) of 20 nm pitch design rule DRAM (Dynamic Random Access Memory) by microwave plasma-enhanced chemical vapor deposition (MW-CVD). We were able to achieve the high phosphorus (CVD gap-fill in a large electrical contact area which does is affected by line pitch size) doping concentration (>2.5 × 10 cm ) and, thus, a low resistivity by adjusting source gas (SiH , H , PH ) decomposition through MW-CVD with a showerhead controlling the decomposition of source gases by using two different gas injection paths. In this study, a selective growth mechanism was applied by using the deposition/etch cyclic process to achieve the bottom–up process in the L-shaped contact, using H plasma that simultaneously promoted the deposition and the etch processes. Additionally, the cyclic selective growth technique was set up by controlling the SiH flow rate. The bottom-up process resulted in a uniform doping distribution, as well as an excellent filling capacity without seam and center void formation. Thus, low contact resistivity and higher transistor on-current could be achieved at a high and uniform phosphorus (P)-concentration. Compared to the conventional thermal, this method is expected to be a strong candidate for the complicated deep and narrow contact process.
机译:低电阻率的多晶硅可以通过微波等离子体增强化学气相沉积(MW-CVD)在20 nm间距设计规则DRAM(动态随机存取存储器)的深(〜200 nm)和窄图案(〜20 nm)中选择性生长。 。我们能够通过调整源气体(SiH)来实现高磷掺杂(在大的电接触区域中进行CVD间隙填充,这确实受线间距尺寸的影响)掺杂浓度(> 2.5×10 cm),从而实现了低电阻率,H,PH)通过喷淋头通过MW-CVD分解,通过两个不同的气体注入路径来控制原料气的分解。在这项研究中,通过使用沉积/刻蚀循环过程来实现自下而上的L形接触,同时促进沉积和刻蚀过程的H等离子体,从而应用了选择性生长机制。此外,通过控制SiH流量建立了循环选择性生长技术。自下而上的过程导致均匀的掺杂分布,以及出色的填充能力,而不会形成接缝和中心空隙。因此,可以在高且均匀的磷(P)浓度下实现较低的接触电阻率和较高的晶体管导通电流。与传统的热法相比,该方法有望成为复杂的深,窄接触过程的理想选择。

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