符合CCSDS标准的动态可重构LDPC编码器的FPGA设计

摘要

CCSDS标准的LDPC生成矩阵具有分块循环特征,并且各种码率的生成矩阵的校验部分都可以分解为8×x的形式,提出利用CCSDS标准的LDPC的特点设计动态可重构LDPC编码器.首先提出了LDPC编码器码速率重构的4种模型,然后分析了功能重构的关键技术模块,最后对码速率重构进行了仿真,并对仿真结果和综合结果进行了分析,结果与理论分析一致.%CCSDS criteria LDPC generator matrix has the characteristic of block circulation, checking part of each code speed generator matrix can be disassembled into the form of 8 X x. According to the characteristic of CCSDS criteria LDPC, Dynamically Reconfigurable LDPC encoder is proposed. Firstly, four models of code speed reconfiguration of LDPC encoder are proposed. Then key technology of function reconfiguration is analyzed. Finally, code speed reconfiguration is simulated, the results of simulation and integration are analyzed which are consistent to theoretical analysis.