CMOS电路IDDQ测试电路设计

摘要

A simple built-in sensor design for quiescent current ( Jddq) testing of CMOS circuits is introduced. By observing the output of the proposed circuit, whether the observed CMOS circuit has the physical defects can be gained. The main part of the proposed circuit is the current differential amplifying circuit, which has an output proportional to JDdq of the observed CMOS circuit . The proposed circuit is connected in series between the observed CMOS circuit and ground for observing the abnormal Iddq < and it comprises 7 transistors and 1 inverter. A simulation is made on the proposed circuit at the transistor level using PSPICE. The validity of the design is tested.%针对CMOS集成电路的故障检测,提出了一种简单的IDDQ静态电流测试方法,并对测试电路进行了设计.所设计的IDDQ电流测试电路对CMOS被测电路进行检测,通过观察测试电路输出的高低电平可知被测电路是否存在物理缺陷.测试电路的核心是电流差分放大电路,其输出一个与被测电路IDDQ电流成正比的输出.测试电路串联在被测电路与地之间,以检测异常的IDDQ电流.测试电路仅用了7个管子和1个反相器,占用面积小,用PSpice进行了晶体管级模拟,实验结果表明了测试电路的有效性.